Error Correction and Detection

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Cortex-R5F processor supports error checking and correction (ECC) data schemes. For each aligned data set, a number of redundant code bits are computed and stored with the data. This enables the processor to detect up to two errors in the data set or its code bits, and correct any single error in the data set or its associated code bits. This is sometimes referred to as a single-error correction, double-error detection (SEC-DED) ECC scheme.