Error Status Register

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

JTAG is the primary method for transmitting error codes out of the device. The error status register connects the error status from the PMU to the JTAG. The data then shifts the status serially out of the device. The error status register is 121-bits long and the output can be masked with an eFUSE for security purposes.

The error status from the PMU is ORed with the eFUSE during the capture phase of the JTAG state machine when the error status instruction is selected. The errors are only masked to the JTAG error status register. The errors can still be read inside the device from the PMU or the PL (depending on the error).

47 bits for hardware errors (these also go to the PL or can be read from the PMU).

74 bits for software errors (these can be read from PMU).

The bits for the error status register are described in Table: JTAG Error Register Description.

Note:   While reading the JTAG_ERROR register, if BISR_failed is asserted, the JTAG_ERROR register must be read again. If it is still asserted after the second read, then this is a true error condition. Otherwise, ignore the first read.