Event Control Timer Operation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The event control timer operates by having an internal 32-bit counter clocked by the LPD_LSBUS_CLK clock that resets to 0 during the non-counting phase of the external pulse and increments during the counting phase of the external pulse.

The event control timer register (TTC.Event_Control_Timer_{0:3}) controls the behavior of the internal counter.

[E_En] bit: When 0, immediately resets the internal counter to 0, and stops incrementing.

[E_Lo] bit: Specifies the counting phase of the external pulse.

[E_Ov] bit: Specifies how to handle an overflow at the internal counter (during the counting phase of the external pulse).

°When 0: Overflow causes [E_En] to be 0 (see the [E_En] bit description).

°When 1: Overflow causes the internal counter to wrap around and continues incrementing.

°When an overflow occurs, an interrupt is always generated (subject to further enabling through another register).

The event register is updated with the non-zero value of the internal counter at the end of the counting-phase of the external pulse. The event register shows the widths of the external pulse, measured in number of cycles of LPD_LSBUS_CLK. If overflow occurs, the event register is not updated and maintains the old value.