Example: Configure and Route Internal Clock for Reference Clock

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Configure the clock and disable MIO path. Assume the PLL is operating at 1000 MHz and the required CAN reference clock is 24 MHz (23.8095 MHz).

1.Program the clock subsystem. Write 0x0030_0E03 to the CRL_APB.CAN0_REF_CTRL register.

a.Enable both CAN reference clocks.

b.Divide the I/O PLL clock by 42 (0x02A): [DIVISOR0] = 0x0E and [DIVISOR1] = 0x03 used by both controllers.

2.Disable the MIO path. Write 0x0000_0000 to the IOU_SLCR.CAN_MIO_CTRL register to select the clock from the internal clock subsystem/PLL for both controllers.