Example: Configure the Interrupts

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

An appropriate handler for the interrupt should be registered with the CPU for processing an interrupt condition. The CPU suspends its normal activity, moves to interrupt processing mode and executes the corresponding handler for an interrupt condition.

1.Register a handler. There are two interrupts generated by the controller: wake-on-LAN and another interrupt for all other functions. Register the handler for each of these interrupt types with the CPU.

Note:   In a typical case, a single handler is used for both transmit and receive.

Once CPU execution reaches the handler, the software should read the gem.int_status register to determine the interrupt source and perform the relevant function.

2.Enable the necessary interrupt conditions. The relevant bits in the gem.int_enable register must be set. The interrupt conditions necessary are determined by the system architecture.

Note:   The read-only register gem.int_mask contains the current state of the interrupt mask each interrupt. If an interrupt bit is asserted in the status register gem.int_status and the corresponding mask bit is disabled, then the IRQ is activated.