1.Wait for the controller to receive a frame. The receive complete interrupt, gem.int_status[receive_complete], is generated when a frame is received.
2.Service the interrupt. Read and clear the gem.int_status[receive_complete] register bit by writing a 1 to the bit in the interrupt handler. Also, read and clear the gem.receive_status register by writing a 1 to gem.receive_status[frame_received] bit.
3.Process the data in the buffer. Scan the buffer descriptor list for the buffer descriptors with the ownership bit, (bit , word ), set. When the DMA receive buffer size programmed to 1,600 bytes (gem.dma_config[rx_buf_size] = 0x19), the packets on the receive side are not scattered and always go into a single buffer. For a buffer descriptor with the ownership bit set, process the buffer allocated in the corresponding buffer descriptor and set the ownership bit to 0. Read other bit fields in the relevant buffer descriptor word , take necessary action, and clear them.