The exception vector pointers (EVP) refer to the base-address of exception vectors (for reset, IRQ, FIQ, etc). The reset-vector starts at the base-address and subsequent vectors are on 4-byte boundaries. The Cortex-R5F processor EVPs are determined as follows.
•If the Cortex-R5F processor SCTRL.V register bit is 0, then exception vectors start from 0x0000_0000 (LOVEC).
•If the Cortex-R5F processor SCTRL.V register bit is 1, then exception vectors start from 0xFFFF_0000 (HIVEC).
The reset value of SCTRL.V is taken from the Cortex-R5F processor VINITHIm pin value, which is driven by the Zynq UltraScale+ MPSoC SLCR bit.
At system boot, the Cortex-R5F processor exception vectors (i.e., VINITHIm pin-value) default to HIVEC, which is mapped in the OCM. The FSBL (running on the Cortex-R5F processor) is expected to change the Cortex-R5F processor exception vectors by changing both the Zynq UltraScale+ MPSoC SLCR to change the value of the VINITHIm pin and the Cortex-R5F processor SCTRL.V bit to LOVEC. The Cortex-R5F processor exception vectors should remain at LOVEC.
RECOMMENDED: AMD does not recommend that you change the exception vector. Changing the EVP to HIVEC will result in increased interrupt latency and jitter. Also, if the OCM is secured and the Cortex-R5F processor is non-secured, then the Cortex-R5F processor cannot access the HIVEC exception vectors in the OCM.