Once the DDRC puts the DDR SDRAM device in deep power-down mode, the DDRC automatically exits deep power-down and repeats the initialization sequence when PWRCTL.deeppowerdown_en is reset to 0. An exit from DFI low power mode is performed prior to exiting deep power-down (this occurs only if DFI low power mode entry during deep power-down entry is successful). DFI low power mode is exited after the wakeup time specified by DFILPCFG0.dfi_lp_wakeup_dpd, but not earlier than DFITMG1.dfi_t_dram_clk_enable + DRAMTMG6.t_ckdpdx clock cycles.
Exiting deep power-down involves these steps when SDRAM initialization is performed by the PHY (INIT0.skip_dram_init = 2’b01 or 2’b11):
2.If step 1 is performed, to ensure that controller updates do not occur when INIT0.skip_dram_init is changed back to 2’b01 (which could make DFI bus active when dfi_ctrlupd_req), it is necessary to set DFIUPD0.dis_auto_ctrlupd and DBG1.dis_hif and to stop sending software controller updates before clearing PWRCTL.deeppowerdown_en.
3.Clear DFIMISC.dfi_init_complete_en = 0 register, before clearing PWRCTL.deeppowerdown_en to ensure that the DDRC waits until the PHY completes its initialization.
4.Reset PWRCTL.deeppowerdown_en to 0 and poll STAT.operating mode to detect when the DDRC exits from DPD and then start the SDRAM initialization by setting the PUB_PIR register.
5.Once PHY Init is started and PIR is programmed, set back the old value of skip_dram_init, if it was updated as described in step 1.
6.Poll the relevant PUB’s PGSR register to detect when the PUB Initialization is complete.
7.Change back the DFIUPD0.dis_auto_ctrlupd and DBG1.dis_hif values and/or restart sending software controller updates, if they were disabled as described in step 2.
8.Set DFIMISC.dfi_init_complete_en = 1 to allow the DDRC’s state machine to exit the initialization state.