Exiting Maximum Power Saving Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Once the DDRC puts the DDR SDRAM device in maximum power saving mode, the DDRC automatically exits maximum power saving mode when PWRCTL.mpsm_en is reset to 0. An exit from DFI low power mode is performed prior to exiting the maximum power saving mode (occurs only if DFI low power mode entry during maximum power saving mode is successful). DFI low power mode is exited after the wakeup time specified by DFILPCFG0.dfi_lp_wakeup_mpsm, but not earlier than DFITMG1.dfi_t_dram_clk_enable + DRAMTMG5.t_cksrx clock cycles (tCKMPX value is the same as tCKSRX).

After exiting maximum power saving mode, geardown should be enabled back by using self-refresh, if it was disabled before MPSM entry.

1.After setting PWRCTL_.mpsm_en to 0, put SDRAM in self-refresh mode by setting PWRCTL.selfref_sw to 1 and polling STAT.operating_mode.

2.Enable back geardown mode by setting MSTR.geardown_mode back to 1.

3.Wake SDRAM up from self-refresh by setting PWRCTL.selfref_sw to 0 and polling STAT.operating_mode (geardown is enabled immediately after self-refresh exit)