FCI Considerations

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

FCI is always disabled.

FCI is configured to flow control the SRC (read) side upon reset.

When FCI is enabled, both the SRC and DST sides use ARLEN for all AXI transactions.

Software configures the FCI interface to the correct side (SRC/DST).

In case of an error, the DMA channel waits until the transaction valid FIFO is empty before going to DONE with an error state.

The DMA channel will stop issuing write commands, if the PL slave does not provide a TACK in response to a TVLD for an extended time and the transaction FIFO goes full.

When the FCI is attached to the DST side, the SRC transactions are limited by the threshold allowed in the common buffer. This threshold can be programmed by the PROG_CELL_CNT of the ZDMA_CH_FCI register in that channel. The DMA channel stops issuing data read commands once the number of occupied cells exceeds the programmed cell count threshold. If the write side of the channel is using FCI and the read side is not controlled, then the channel uses most of the common buffer. This limits the other channels. By using the threshold on common buffer usage, the channel's usage of the common buffer can be controlled.

Once the channel is enabled with the FCI, the DMA channel accumulates incoming credits. Each channel can accumulate up to 32 credits. Each transaction consumes one credit. Channel will not issue a new transaction if credit is not available. Credit is consumed upon generation of read/write commands based on the FCI configuration. If the FCI is not enabled, it does not affect the generation of AXI commands on the SRC/DST.

The FCI accepts credit from the PL slave as long as the credit FIFO is not full. Credits are flushed until the channel is enabled. Once a channel is enabled, a DMA channel uses credits to flow control the SRC/DST AXI commands. In the event of an error, the DMA channel performs an error-recovery sequence. Once done with error recovery, the channel clears both the FCI_EN and channel EN flags. Once it clears the FCI_EN, the DMA channel flushes all available and incoming credits until the next peripheral enable. The software provides channel state information to the PL slave (enable, pause, and error).

The DMA channel provides a transaction valid notification to the PL slave on every AXI write transaction completion. A transaction valid is always generated on receiving a valid BRESP. Irrespective of any read/write association, a transaction valid always indicates completion of a write transaction. Software can calculate and provide the total number of valid transactions expected to complete the current DMA transaction to PL slave. PL slave can use a transaction valid to find where a DMA channel is in a current DMA transaction.