FIFO Interface Timing Criteria

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This Figure shows the detailed timing relationships for a frame on the FIFO interface (MAC transmit) with one cycle between the read request and data valid.

Figure 34-3:      FIFO Interface (MAC Transmit) with One Cycle

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This Figure shows the detailed timing relationships for a frame on the FIFO interface (MAC transmit) that incorporates a 2-byte frame with an SOP and an EOP in the same transfer.

Figure 34-4:      FIFO Interface (MAC Transmit) with SOP and EOP in the Same Transfer

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This Figure shows the detailed timing relationships for a frame on the FIFO interface (MAC transmit) with a frame error.

Figure 34-5:      FIFO Interface (MAC Transmit) with a Frame Error

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This Figure shows a frame on the FIFO interface (MAC receive).

Figure 34-6:      FIFO Interface (MAC Receive)

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This Figure shows a frame on the external FIFO interface (MAC receive) with a frame error.

Figure 34-7:      FIFO Interface (MAC Receive) with a Frame Error

X-Ref Target - Figure 34-7

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Note:   A FIFO output signal (tx_r_fixed_lat) is generated by the FIFO adapter to signal to the 8-bit FIFO interface when the latency on that internal interface is fixed. Only when the tx_r_fixed_lat signal is asserted can the latency through the design be assumed as fixed, then used to insert the correction field and/or timestamp fields into the datastream. For a 32-bit MAC datapath, the output signal is asserted later than the 22nd read on the 8-bit FIFO interface (mapping to offset 22 in the Ethernet frame). Only the assertion of this signal is of value, your design logic should detect the rising edge of this signal to determine when latency is fixed and ignore the deassertion.