FIFO Interface to PL

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Data is transmitted and received via the GEM RXFIFO and TXFIFO. There are two ways to access the FIFOs:

GEM DMA engine as a master on the PS AXI interconnect (LPD) with a 32-bit data access width.

   Slave interface in the PL via the external FIFO interface with an 8-bit data access width.

The access to the FIFOs is selected by the GEM.external_fifo_interface [external_fifo_interface] register bit.