The status bits for the FIFO interrupts listed in Table: UART Interrupt Status Bits are illustrated in This Figure. These interrupt status bits are in the Channel Status (uart.Channel_sts) and Channel Interrupt Status (uart.Chnl_int_sts) registers.
The FIFO trigger levels are controlled by these bit fields:
•uart.Rcvr_FIFO_trigger_level[RTRIG], a 6-bit field
•uart.Tx_FIFO_trigger_level[TTRIG], a 6-bit field