FPD-PL Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section describes the PL to PS interfaces going into the full-power domain (FPD).

Six high-performance interfaces provide the PL bus masters access to all PS slaves. However, these are designed to provide high-bandwidth datapaths to the DDR memory.

Two high-performance masters from the FPD into the PL. Primarily these are used by high-performance PS masters like the APU, FPD DMA, and PCIe.