FPD Reset Sequence

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The FPD-reset resets all of the full-power domain (FPD). It can be triggered by errors or a software register write. If the FPD reset is due to an error signal, then the error must also be indicated to the LPD and the PL. The FPD reset can be primed by leveraging the FPD power-up sequence. However, it needs to gracefully terminate the FPD ingress/egress AXI transactions before initiating reset of the FPD. The FPD reset sequence can be produced as follows.

An error interrupt is asserted a FPD reset is required. This request is sent to the PMU as an interrupt.

Block the FPD to LPD interfaces with the help of the AIB.

If an AIB acknowledgment is not received, then the PMU should timeout and continue.

Block the FPD to PL interfaces with the help of the AIB (in the FPS).

If the AIB acknowledgment is not received, then the PMU should timeout and continue.

Block the LPD to FPD interfaces with the help of the AIB.

Block the PL to FPD interfaces with the help of the AIB (in PL design). The PL wrapper should provide a timeout between this AIB and the FPD.

Assert the FPD reset (by writing to a PMU global register).

Unblock the FPD to LPD and FPD to PL interfaces.

Deassert the FPD reset (including CCI), which enables the LPD requests to go to the FPD.

Unblock the LPD to FPD and the PL to FPD interfaces.

Deassert the APU L2/CPU resets, which results in an APU reboot.