Features

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

JTAG Chain:

Single JTAG chain: one, two, or all three TAP controllers.

Split JTAG chain: PS/PL TAP controllers and Arm DAP controller.

Triple redundant JTAG security controls.

PS TAP controller:

IDCODE access.

PL TAP and Arm DAP controller insertion.

PS error-code read out.

System JTAG controls.

PL TAP controller:

Boundary-scan.

Legacy PL configuration.

Legacy PL debug (Vivado logic analyzer).

Arm DAP controller:

The DAP can be accessed directly in any non-secure boot mode. In secure boot mode, the DAP is not accessible unless trusted software enables the JTAG connection for the DAP controller.

Arm DAP requires the VCC_PSINTLP power supply.

Nonvolatile flash programming.

PS CoreSight debug architecture support.

PS eFUSE and BBRAM programming.

Access to AXI interconnect.

Security:

PSJTAG interface signal tamper detection.

Always secure from reset to boot header processing.

JTAG state machines:

Interfaces are compatible with the IEEE Std 1149 specification.

All states transition on the positive edge of TCK.

Interfaces are controlled by the TMS signal.

IDCODE instruction:

Indicates the type of device: device ID codes are listed in Table: Device ID Codes and Minimum Production Revisions.

Requires LPD to be powered up, but not the PLPD or FPD.

Always accessible regardless of security state.

 

Figure 39-1:      JTAG Chain Block Diagram

X-Ref Target - Figure 39-1

X19944-jtag-block-diagram.jpg