Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.3.1 English

Key features of the GPIO peripheral are summarized as follows:

78 GPIO interfaces to the device pins.

°Routed through the MIO multiplexer.

°Programmable I/O drive strength, slew rate, and 3-state control.

96 GPIO interfaces to the PL (four allocated by software to reset PL logic).

°Routed through the EMIO interface.

°Data inputs.

°Data outputs.

°Output enables.

I/O interface is organized into six banks (3 MIO and 3 EMIO).

Interface control registers are grouped by bank {0:5}.

Input values are read using the six DATA_RO_x registers.

Two types of data ports for writing:

°Full bank write using the DATA_x registers.

°Split bank maskable write using the MASK_DATA_x_{LWS, MWS} register pairs.

The function of each GPIO can be dynamically programmed on an individual or group basis.

Enable, bit or bank data write, output enable and direction controls.

Programmable interrupts on individual GPIO basis.

°Status read of raw and masked interrupt

°Selectable sensitivity: Level-sensitive (High or Low) or edge-sensitive (positive, negative, or both).