Flow Control Interface

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
Release Date
2.3 English

Data transactions on the AXI write channel can only be controlled using the flow-control interface (FCI). The FCI is implemented per channel to provide read/write access flow control ability to the PL slave. The FCI can be independently controlled from each channel's control register. Software configures what accesses are flow controlled by the FCI (read/write).

The PL slave provides credits to the DMA channel. Each credit is a permission for a single AXI transaction. When the FCI is attached to the SRC (read), there is a permission to generate one AXI data read transaction (write transaction when FCI is attached to DST (write)). Table: Flow Control Interface Signals lists the FCI signals.


IMPORTANT:   The maximum number of credits accepted are 32.

Table 19-4:      Flow Control Interface Signals




PL clock: Signals from/to PL are synchronous to pl2dma_clk. The DMA handles all clock domain crossing.


Credit valid


Credit acknowledgment:

Credits are accumulated when both pl2dma_cvld and dma2pl_cack are High (TRUE).

Each FCI can accumulate up to 32 credits.

If the FCI is not enabled, the credits are flushed.


Transaction valid


Transaction acknowledgment: The DMA channel indicates that one write transaction is done (AXI write command was generated and a BRESP is received) when TVLD and TACK are TRUE.

The timing diagram for the flow control interface is as shown in This Figure.

Figure 19-5:      FCI Flow Control Interface

X-Ref Target - Figure 19-5


Software can configure FCI to flow control either the SRC or DST based on whether the DMA channel is reading from or writing to the PL slave.

FCI must be configured to flow control SRC if the DMA is reading from the PL slave.

FCI must be configured to flow control DST if the DMA is writing to the PL slave.