Fractional Multiply and Divide Programming Example

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The following example assumes that the input clock to the PLL is PS_REF_CLK at 50 MHz, the FBDIV value is 32, and the output divider is turned on. The output frequency is 1600 MHz. To change to the VIDEO_REF_CLK, which is at 27 MHz and produce a final frequency of 1090.125 MHz, the FBDIV divider must be 40.375. Because 1090.125 MHz is below the VCO operating range, a value of 80.75 is required and the div2 is used to produce 1090.125 MHz. This example uses the VPLL.

1.Program the bypass mode by configuring VPLL_CTRL[BYPASS] = 1.

2.Program the new FBDIV, CLKOUT, and PRE_SRC values.
VPLL_CTRL[DIV2] = 1
VPLL_CTRL[FBDIV] = 50h
VPLL_CTRL[PRE_SRC] = 100b: VIDEO_REF_CLK

3.Program the VPLL_CFG register. Refer to the VPLL_CFG programming helper data in Table: PLL Integer Feedback Divider Helper Data Values.

4.Program the fractional data. A value of 0.75 = 0Bh.
VPLL_FRAC_CFG[ENABLED] = 1
VPLL_FRAC_CFG[DATA] = C000h
VPLL_FRAC_CFG = 8000_C000h

5.Assert the reset. This is required when the new data is actually captured into the PLL. VPLL_CTRL[RESET] = 1

6.Deassert the reset.
VPLL_CTRL[RESET] = 0

7.Check for a locked signal.

8.Wait until: PLL_STATUS[VPLL_LOCK] = 1

9.Deassert the bypass.
VPLL_CTRL[BYPASS] = 0

Similar steps are followed to program DPLL, RPLL, IOPLL, and APLL.