Functional Units and Peripherals

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table: Functional Units and Peripherals lists and describes the main functional units and peripherals.

Table 1-1:      Functional Units and Peripherals

Name

Description

APU MPCore

Application processing units: two or four 64-bit Cortex-A53 processors, supports four exception levels, NEON instructions, and single/double precision floating-point calculations, includes accelerator port (ACP) and AXI coherency extension (ACE), snoop-control unit (SCU), and L2 cache controller (CG devices are dual core, all others are quad).

RPU MPCore

Real-time processing units: dual 32-bit Cortex-R5F processor, Arm instruction set, dynamic branch prediction, redundant CPU logic for fault detection, 32/64/128-bit AXI interface to the PL for low-latency applications.

GPU

Graphics processing units: one geometry processor, two pixel processors, OpenGL ES 1.1 and 2.0, OpenVG 1.1, advanced anti-aliasing support (available in the EG and EV product families).

VCU

The video codec unit (VCU) provides multi-standard video encoding and decoding, including support for the high-efficiency video coding (HEVC) H.265 and advanced video coding (AVC) H.264 standards. The unit contains both encode (compress) and decode (decompress) functions, and is capable of simultaneous encode and decode. The VCU is included in the EV product family of the MPSoC devices.

RF

The RF-ADC, RF-DAC, and soft-decision FEC functions are located in the PL. These RF circuits enable software-defined radios using the direct RF sampling data converters to enable CPRI™ and gigabit Ethernet-to-RF functionality. The RF unit is included in the DR product family exclusively part of the RFSoC devices.

AMBA interconnect

AXI cache-coherent interconnect, interconnects belonging to two power domains, (central switch and low-power switch), processing system to programmable logic interface.
APB buses for register access, AHB for some IOP masters.

CSU

Configuration security unit: triple redundant processor for controlling; supports secure and non-secure boot flows.

System interrupts

Processor, controller, and other system element interrupts. Inter-processor interrupts (IPI). Software generated interrupts. RPU and APU interrupts and system interrupts. Inter-processor interrupt, support for software generated interrupt and shared peripheral interrupt.

TTC

4x Triple Timer Counters: programmable 32-bit and 64-bit timers, programmable event counters.

LPD and FPD DMA units

Programmable number of outstanding transfers, support for simple and scatter-gather mode, support for read-only and write-only DMA mode, descriptor prefetching, per channel flow control interface.

DDR memory controller

DDR3, DDR3L, DDR4, LPDDR4, up to two ranks, dynamic scheduling to optimize bandwidth and latency, error-correction code support in 32-bit and 64-bit mode, software programmable quality of service.

NAND memory controller

Complies with ONFI 3.1 specification, supports reset logical unit number, ODT configuration, on-die termination.

SPI controller

Full duplex operation, multi-master environment support, programmable master mode clock frequency, programmable transmission format.

Quad-SPI controller

Stacked and parallel modes, supports command queuing, supports 4/8 bit interface, 32-bit address support on AXI in DMA mode transfer.

CAN controller

Standard and extended frames, automatic retransmission on errors, four RX acceptance filters with enables, masks, and IDs.

UART controller

Programmable baud rate generator, 6/7/8 data bits, modem control signals.

I2C controller

I2C bus specification version 2.0 supported, normal and fast mode transfer, slave monitor mode.

SD/SDIO/eMMC controller

Data transfer in 1-bit or 4-bit mode, cyclic redundancy check for data and command, card insertion/removal detection.

GPIO

78 GPIO signals for device pins, 96 GPIO channels between PS and PL, programmable interrupt on individual GPIO channel.

PL peripherals

Peripherals present in the PL:

PCI Express rev 3.1 and 4.0.

Interlaken

100G Ethernet

PL System Monitor

Video encoder/decoder (VCU is available in EV MPSoC devices).

High-speed transceivers (up to 32.75 Gb/s)

DisplayPort audio and video interface

RF I/O subsystem (RFSoC devices)

Platform management unit

System initialization during boot, management of power gating and retention states, management of sleep states, triple-redundant processor.

Clock system

Five independent system PLLs used as clock source for a few dozen clock generators for all the functional units and peripherals.

Reset system

Individual peripheral level reset generation, PS only reset.

Arm DAP controller

Access to debug access port and Arm CoreSight components.

Arm CoreSight debug components

Break-point and single stepping, AXI trace monitor to capture AXI transactions, CoreSight system trace macrocell (STM) captures software driven traces, CoreSight extension from the PL.

On-chip memory (OCM)

256KB RAM, very high throughput support on AXI interconnect, ECC support.

Tightly-coupled memory

Four TCM banks, each one is 64 KB.

PS-GTR transceivers

Compliant with PCIe 2.0, USB 3.0, DisplayPort 1.2a, SATA 3.1, and SGMII protocols, internal PLL per lane to support multiple protocols, integrated termination resistors, BIST, and supports loopbacks as required by the supported protocols.

PCI Express rev 2.1

End Point and Root Port mode, Gen1 and Gen2 rates, MSI, MSI-X, and legacy interrupt support, AXI PCIe bridge, integrated four-channel fully-configurable DMA.

USB controller

USB 2.0/3.0 host, device, OTG, 5 Gb/s data rate, AXI master port with built-in DMA, power management feature, hibernation mode, simultaneous operation of USB 2.0 and 3.0.

SATA host controller

Compliant with the SATA 3.1 specification, supports 1.5G, 3G, and 6G line rates, compliant with the advanced host controller interface version 1.3. The controller has an embedded DMA that facilitates memory transfers.

DisplayPort interface

Source only controller with an embedded DMA controller that supports 1G or 2G transceiver lanes, supports real-time video and audio input from the PL.

Gigabit Ethernet controller and serial GMII (GEM)

IEEE Std 802.3-2008 compatible, full and half-duplex modes of operation, RGMII/SGMII interface support, MDIO interface, automatic discard frames with errors, programmable inter packet gap, full-duplex flow control. The controller has a built in DMA engine that can be used to transfer Ethernet packets from memory.

System protection units

Memory and peripheral partitioning and protection, TrustZone protection, error handling on permission violation/disallowed transactions, access control for a specific range of addresses, access control on a per-peripheral basis.