GIC Address Map

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The APU GIC's base address is configured by the APU MPCore pins (PERIPHBASE). The RPU GIC's base address is aligned to the Cortex-R5F MPCore’s low-latency peripheral port (LLPP) base-address.

The GIC-400 uses eight pages of 4 KB memory-mapped address-space. However, to support a 64 KB page size (as required by SBSA v2), the GIC-400 address needs to be mapped such that pages are 64 KB. For this, the AXI address is mapped to a GIC slave interface as described in this equation.

AddressGIC400[14:0] = {AddressAXI[18:16], AddressAXI[11:0]}