Generate an Interrupt

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

To generate an interrupt, the sender writes a 1 to a bit in its trigger (TRIG) register that corresponds to the target receiver. It can verify that a bit is set in the receiver's status register by reading its own OBS register. However, it cannot determine if the interrupt is enabled to generate the IRQ interrupt signal.