Generic Quad-SPI Commands

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table: Generic Quad-SPI Controller: SPI Mode Commands lists the fields used for programming the generic FIFO for different SPI commands when the generic Quad-SPI controller is used for SPI mode commands and only the lower data bus is used. When needed, the other fields (poll, stripe, and exponent) can be programmed.

Table 24-4:      Generic Quad-SPI Controller: SPI Mode Commands

SPI Command

Receive

Transmit

Data Bus
Select

cs_upper

cs_lower

SPI Mode

data
_xfer

immediate_data

Description

CS assert

1'b0

1'b0

2'b01

1'b0

1'b1

2'b01

1'b0

8'h04
(CS setup Time)

Assert lower chip select (CS).

The immediate_data field specifies the value of the CS setup time (tCSS). Because the value is 8’h04, the CS setup time is four QSPI_REF_CLK cycles.

In SPI mode, the receive and transmit are not considered. The data bus select and cs_upper and cs_lower should be valid values.

read

1'b1

1'b0

2'b01

1'b0

1'b1

2'b01

1'b1

8'h34
(52 read data bytes)

Read lower data bus.

The immediate_data field specifies the number of data bytes read. Because the value is 8’h34, the number of data bytes received is 52 bytes.

write immediate

1'b0

1'b1

2'b01

1'b0

1'b1

2'b01

1'b0

8'h64

Write lower data bus immediate.

The immediate_data field specifies the data to be written. Because the value is 8'h64, the data sent on the SPI is 8'h64.

write

1'b0

1'b1

2'b01

1'b0

1'b1

2'b01

1'b1

8'h64
(100 write data bytes)

Write lower data bus. The immediate_data field specifies the number of write data bytes. Because the value is 8'h64, the number of data bytes written is 100 bytes.

read_write immediate

1'b1

1'b1

2'b01

1'b0

1'b1

2'b01

1'b0

8'h64

Read and write lower data bus immediate.

The immediate_data field specifies the data to be written. Because the value is 8'h64, the data sent on the SPI is 8'h64. When receive is set to 1, one data byte is received and stored in the RXFIFO.

read_write

1'b1

1'b1

2'b01

1'b0

1'b1

2'b01

1'b1

8'h64 
(100 read and write data bytes)

The read and write lower data bus.

The immediate_data field specifies the number of write and read data bytes. Because the value is 8'h64, the number of data bytes received is 100 bytes and transmitted is also 100 bytes.

dummy

1'b0

1'b0

2'b01

1'b0

1'b1

2'b01

1'b1

8'h06
(six dummy SCLK cycles)

Inserts dummy cycles on lower data bus.

The immediate_data field specifies the number of dummy SCLK cycles. Because the value is 8'h06, the number of dummy cycles is six. Data bus select, data_xfer and cs_upper, and cs_lower should be valid values. The data bus select value during the dummy phase should be same as the data phase.

CS deassert

1'b0

1'b0

2'b01

1'b0

1'b0

2'b01

1'b0

8'h06

Deassert the lower chip select.

The immediate_data field specifies the value of the chip select hold time (tCSH). Because the value is 8'h06, the chip select hold time is five reference clock cycles (one less than the specified value (6-1 = 5)). SPI mode, receive, and transmit are not considered. The data bus select should be valid. The minimum immediate_data field should be four.