Generic Timer Programming

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Memory-mapped controls of the system counter are accessible only through the memory-mapped interface to the system counter.

These controls are listed.

Enabling and disabling the counter.
CNTCR, counter control register EN, bit [0]:

°0: System counter disabled.

°1: System counter enabled.

Setting the counter value.
Two contiguous RW registers CNTCV [31:0] and CNTCV [63:32] that hold the current system counter value, CNTCV. If the system supports 64-bit atomic accesses, these two registers must be accessible by such accesses.

Changing the operating mode to change the update frequency and increment value.
CNTCR, counter control register FCREQ, bits [17:8]: frequency change request.

Enabling halt-on-debug for a debugger to use to suspend counting.
CNTCR, counter control register HDBG, bit [1]: Halt-on-debug. Controls whether a halt-on-debug signal halts the system counter:

°0: System counter ignores halt-on-debug.

°1: Asserted halt-on-debug signal halts system counter update.