Glitch Filter

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The I2C bus specification specifies that 50 ns glitches should be removed from the clock and data signals. The I2C controller provides a digital glitch filter for filtering glitches on the SDA and SCL inputs. The filter is built using a shift register and the filter length is specified in terms of APB interface clock cycles (LPD_LSBUS_CLK). The glitch filter control register Glitch_Filter is used to set the length of the glitch filter shift register. The appropriate value written into the Glitch_Filter register allows for the removal of 50 ns glitches. Consequently, the value written into the Glitch_filter_reg.GF register should be equal to the number of APB clock cycles that gives a total length of 50 ns. The default value is five. If the length of the glitch filter shift register is set to zero, then the glitch filter is bypassed.