Graphics Processing Unit Level 2 Cache Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The advanced peripheral bus (APB) slave controls the Level 2 cache controller through various commands.

APB slave provides an interface to enable bus masters to control the Level 2 cache. The APU MPCore or other AXI bus master can write into the cache controller. The graphics driver seamlessly supports these connections.

Arbiter accepts memory access requests into a circulating loop. They circulate in the loop until the access router determines that they can be removed.

Tag accessor performs a cache lookup to determine if data is in the cache.

Access router for each read or write request matching the AXI ID and the timestamp of the current request against all other requests in the loop.

Replay buffer that handles all request collisions of data.

Cache tags unit holds a pipelined SRAM for the cache tags.

Cache line fetcher draws the external data from the AXI master interface.

Cache SRAM is the actual data store of the cache.

The Level 2 cache controller performs the tasks shown in Table: Level 2 Cache Controller Tasks.

Table 5-3:      Level 2 Cache Controller Tasks

Controller Task

Description

Looping

Memory requests enter by the arbiter and keep circulating in a loop until the access router determines they can be taken out of the loop.

Cache tag lookup

For each request, the tag accessor performs a cache lookup to see if data is in the cache. The cache tags are kept in a single SRAM within this sub-unit. It is fully pipelined and permits one tag operation to be performed per clock cycle. A tag operation consists of a lookup, tag-write, and line-invalidate.

Access routing

The access router passes data for each request to the read buffer, write buffer or replay buffer.

Handling data collisions

The replay buffer handles all request collisions of data. These request collisions, also called bad-hits, continue to loop around the system until the access router determines when they can be taken out of the loop.

Storing cache tags

The cache tags unit holds a pipelined SRAM for the cache tags. The cache tags are stored in a single SRAM within this sub-unit.

The Level 2 cache controller is a configurable cache controller able to manage 16 KB to 16 MB of Level 2 cache RAM. It is a four-way set-associative cache controller with a pseudo-least recently used (LRU) replacement algorithm that yields great bandwidth savings in graphics operations. It supports high throughput, out of order data transactions within the AXI protocol limits, and up to 32 outstanding transactions and 64-byte bursts.

Because the Level 2 is a specialized cache controller for use with Mali GPUs, the following limitations apply.

Write data is not cached because it does not increase memory bandwidth or performance savings.

Writes to any cached location cause the relevant cache line to be cleared.

Only incremental bursts are supported, there is no support for unaligned, fixed, and wrapping bursts.

AXI slave ports are fixed at 64-bits wide. The AXI master port is configurable to be either 64 bits or 128 bits.

The main part of the cache controller is a loop of the four sub-modules.

Arbiter

Tag accessor

Access router

Replay buffer