Graphics Processing Unit Register Overview

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table: GPU Register Summary is an overview of the GPU registers.

Table 5-5:      GPU Register Summary

Register Type

Register Name

Description

Geometry Processor Control Registers

GP_CONTR_REG_VSCL_START_ADDR

GPU control register VSCL start address

GP_CONTR_REG_VSCL_END_ADDR

GPU control register VSCL end address

GP_CONTR_REG_PLBCL_START_ADDR

GPU control register PLBCL start address

GP_CONTR_REG_PLBCL_END_ADDR

GPU control register PLBCL end address

GP_CONTR_REG_PLB_ALLOC_START_ADDR

GPU control register PLB allocate start address

GP_CONTR_REG_PLB_ALLOC_END_ADDR

GPU control register PLB allocate end address

GP_CONTR_REG_CMD

GPU control register command

GP_CONTR_REG_INT_RAWSTAT

GPU control register interrupt raw interrupt status

GP_CONTR_REG_INT_CLEAR

GPU control register interrupt clear

GP_CONTR_REG_INT_MASK

GPU control register interrupt mask

GP_CONTR_REG_INT_STAT

GPU control register interrupt status

GP_CONTR_REG_WRITE_BOUND_LOW

GPU control register write boundary Low

GP_CONTR_REG_WRITE_BOUND_HIGH

GPU control register write boundary High

GP_CONTR_REG_PERF_CNT_0_ENABLE

GPU control register performance counter 0 enable

GP_CONTR_REG_PERF_CNT_1_ENABLE

GPU control register performance counter 1 enable

GP_CONTR_REG_PERF_CNT_0_SRC

GPU control register performance counter 0 source

GP_CONTR_REG_PERF_CNT_1_SRC

GPU control register performance counter 1 source

GP_CONTR_REG_PERF_CNT_0_VAL

GPU control register performance counter 0 value

GP_CONTR_REG_PERF_CNT_1_VAL

GPU control register performance counter 1 value

GP_CONTR_REG_PERF_CNT_0_LIMIT

GPU control register performance counter 0 limit

GP_CONTR_REG_PERF_CNT_1_LIMIT

GPU control register performance counter 1 limit

GP_CONTR_REG_STATUS

GPU control register status

GP_CONTR_REG_VERSION

GPU control register version

GP_CONTR_REG_VSCL_INITIAL_ADDR

GPU control register VSCL initial address

GP_CONTR_REG_PLBCL_INITIAL_ADDR

GPU control register PLBCL initial address

GP_CONTR_REG_WRITE_BOUNDARY_
ERROR_ADDR

GPU control register write error address

GP_CONTR_REG_AXI_BUS_ERROR_STAT

GPU control AXI bus error status

GP_CONTR_REG_WATCHDOG_DISABLE

GPU control register watchdog disable

GP_CONTR_REG_WATCHDOG_TIMEOUT

GPU control register watchdog timeout

Control Register

VERSION

Version register

SIZE

Size register

STATUS

Status register

COMMAND

Command register

CLEAR_PAGE

Clear page register

MAX_READS

Maximum reads register

ENABLE

Enable register

Performance Counter Register

PERFCNT_SRC0

Performance counter 0 source register

PERFCNT_VAL0

Performance counter 0 value register

PERFCNT_SRC1

Performance counter 1 source register

PERFCNT_VAL1

Performance counter 1 value register

Geometry Processor MMU Control Register

GP_MMU_DTE_ADDR

MMU current page table address register

GP_MMU_STATUS

MMU status register

GP_MMU_COMMAND

MMU command register

GP_MMU_PAGE_FAULT_ADDR

MMU logical address

GP_MMU_ZAP_ONE_LINE

MMU zap-cache line register

GP_MMU_INT_RAWSTAT

MMU raw interrupt status register

GP_MMU_INT_CLEAR

MMU interrupt clear register

GP_MMU_INT_MASK

MMU interrupt mask register

GP_MMU_INT_STATUS

MMU interrupt status register

Pixel Processor MMU Control Register

[x = 0, 1]

PPx_MMU_DTE_ADDR

MMU current page table address register

PPx_MMU_STATUS

MMU status register

PPx_MMU_COMMAND

MMU command register

PPx_MMU_PAGE_FAULT_ADDR

MMU logical address

PPx_MMU_ZAP_ONE_LINE

MMU zap-cache line register

PPx_MMU_INT_RAWSTAT

MMU raw interrupt status register

PPx_MMU_INT_CLEAR

MMU interrupt clear register

PPx_MMU_INT_MASK

MMU interrupt mask register

PPx_MMU_INT_STATUS

MMU interrupt status register

Pixel Processor Render And Tile Buffer Control Register

[x = 0, 1]

PPx_REND_LIST_ADDR

Renderer list address register

PPx_REND_RSW_BASE

Renderer state word base address register

PPx_REND_VERTEX_BASE

Renderer vertex base register

PPx_FEATURE_ENABLE

Feature enable register

PPx_Z_CLEAR_VALUE

Z clear value register

PPx_STENCIL_CLEAR_VALUE

Stencil clear value register

PPx_ABGR_CLEAR_VALUE_0

Alpha-blue-green-red (ABGR) clear value 0 register

PPx_ABGR_CLEAR_VALUE_1

ABGR clear value 1 register

PPx_ABGR_CLEAR_VALUE_2

ABGR clear value 2 register

PPx_ABGR_CLEAR_VALUE_3

ABGR clear value 3 register

PPx_BOUNDING_BOX_LEFT_RIGHT

Bounding box left right register

PPx_BOUNDING_BOX_BOTTOM

Bounding box bottom register

PPx_FS_STACK_ADDR

Fault status (FS) stack address register

PPx_FS_STACK_SIZE_AND_INIT_VAL

Fault status (FS) stack size and initial value register

PPx_ORIGIN_OFFSET_X

Origin offset X register

PPx_ORIGIN_OFFSET_Y

Origin offset Y register

PPx_SUBPIXEL_SPECIFIER

Sub-pixel specifier register

PPx_TIEBREAK_MODE

Tie-break mode register

PPx_PLIST_CONFIG

Polygon list format register

PPx_SCALING_CONFIG

Scaling register

PPx_TILEBUFFER_BITS

Tile-buffer configuration register

Write-Back Buffer Control Register

[x = 0, 1]

[y = 0, 1, 2]

PPx_WBy_SOURCE_SELECT

Write-back y source select register

PPx_WBy_TARGET_ADDR

Write-back y target address register

PPx_WBy_TARGET_PIXEL_FORMAT

Write-back y target pixel format register

PPx_WBy_TARGET_AA_FORMAT

Write-back y target anti-aliasing format register

PPx_WBy_TARGET_LAYOUT

Write-back y target layout

PPx_WBy_TARGET_SCANLINE_LENGTH

Write-back y target scan-line length

PPx_WBy_TARGET_FLAGS

Write-back y target flags register

PPx_WBy_MRT_ENABLE

Write-back y multiple render target (MRT) enable register

PPx_WBy_MRT_OFFSET

Write-back y MRT offset register

PPx_WBy_GLOBAL_TEST_ENABLE

Write-back y global test enable register

PPx_WBy_GLOBAL_TEST_REF_VALUE

Write-back y global test reference value register

PPx_WBy_GLOBAL_TEST_CMP_FUNC

Write-back y global test compare function register

Pixel Processor Misc Control Register

[x = 0, 1]

PPx_VERSION

Version register

PPx_CURRENT_REND_LIST_ADDR

Current renderer list address register

PPx_STATUS

Pixel processor status register

PPx_CTRL_MGMT

Control management register

PPx_LAST_TILE_POS_START

Last tile where processing started register

PPx_LAST_TILE_POS_END

Last tile where processing completed register

PPx_INT_RAWSTAT

Interrupt raw status register

PPx_INT_CLEAR

Interrupt clear register

PPx_INT_MASK

Interrupt mask register

PPx_INT_STATUS

Interrupt status register

PPx_WRITE_BOUNDARY_ENABLE

Write boundary enable register

PPx_WRITE_BOUNDARY_LOW

Write boundary Low register

PPx_WRITE_BOUNDARY_HIGH

Write boundary High register

PPx_WRITE_BOUNDARY_ADDRESS

Write boundary address register

PPx_BUS_ERROR_STATUS

Bus error status register

PPx_WATCHDOG_DISABLE

Watchdog disable register

PPx_WATCHDOG_TIMEOUT

Watchdog time-out register

Pixel Processor's Performance Counter Registers

PPx_PERF_CNT_0_ENABLE

Performance counter 0 enable register

PPx_PERF_CNT_0_SRC

Performance counter 0 system reset controller (SRC) register

PPx_PERF_CNT_0_LIMIT

Performance counter 0 limit register

PPx_PERF_CNT_0_VALUE

Performance counter 0 value register

PPx_PERF_CNT_1_ENABLE

Performance counter 1 enable register

PPx_PERF_CNT_1_SRC

Performance counter 1 system reset controller register

PPx_PERF_CNT_1_LIMIT

Performance counter 1 limit register

PPx_PERF_CNT_1_VALUE

Performance counter 1 value register

PPx_PERFMON_CONTR

Performance monitor control register

PPx_PERFMON_BASE

Performance monitor base address register