Group 1: Registers that can be written when no read/write traffic is present at the DFI

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

By setting the DBG1.dis_dq register and polling DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty1, it is possible to prevent any read or write traffic from being sent on the DFI. Also, if DDR4 retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, poll CRCPARSTAT.cmd_in_err_window until it is equal to 0. If software intervention is enabled by CRCPARCTL1.alert_wait_for_sw, also monitor CRCPARSTAT.dfi_alert_err_int and CRCPARSTAT.dfi_alert_err_fatl_int during the polling. If one or more of them are asserted before polling is done, retry procedure must be completed prior to the subsequent steps. In this mode, it is safe to write to the group 1 registers.

Re-enable the traffic by writing DBG1.dis_dq to 1’b0. To make sure the correct value is propagated, registers DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipe-line_empty must be polled at least twice after DBG1.dis_dq is set to 1.