Group 2: Registers that can be written in self-refresh, DPD, and MPSM modes

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When the DDRC has entered self-refresh mode via software (PWRCTL.selfref_sw), the DFI bus is idle until software exits self-refresh. The same is true in deep power-down (DPD) for LPDDR3, and maximum power saving mode (MPSM) for DDR4.

Note:   For self-refresh, ensure that self-refresh is not caused by “Automatic Self-refresh only” by checking the STAT.operating_mode = 3’b011 and STAT.selfref_type = 2’b10. If DDR4 retry is enabled by CRCPARCTRL1.crc_parity_retry_enable and software intervention is enabled by CRCPARCTL1.alert_wait_for_sw, also monitor CRCPARSTAT.dfi_alert_err_int and CRCPARSTAT.dfi_alert_err_fatl_int during the polling STAT.selfref_type. If one or more of them are asserted before polling is done, retry procedure must be completed prior to the subsequent steps.

In this section, references to self-refresh mean self-refresh (non-LPDDR4), or SR-Powerdown (LPDDR4).

For MPSM, ensure STAT.operating_mode = 3’b110 is the case before changing any of the registers listed below (see explanation below). If DDR4 retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, poll CRCPARSTAT.cmd_in_err_window until it equals 0. If software intervention is enabled by CRCPARCTL1.alert_wait_for_sw, also monitor CRCPARSTAT.dfi_alert_err_int and CRCPARSTAT.dfi_alert_err_fatl_int during the polling. If one or more of them are asserted before polling, retry procedure must be completed prior to the subsequent steps.

For DPD, ensure STAT.operating_mode = 3’b110 is the case before changing any of the registers listed below (see the explanation below).

STAT.operating_mode = 3’b1xx for DPD/MPSM, but entry/exit and in mode itself can be differentiated as follows:

°operating_mode = 3’b101 — DPD/MPSM entry is occurring.

°operating_mode = 3’b110 — DPD/MPSM mode is reached.

°operating_mode = 3’b111 — DPD/MPSM exit is occurring.

In this mode, it is safe to write the group 2 registers.

Re-enable the traffic by writing PWRCTL.selfref_sw to 1’b0.