Group 3: Registers that can be written when controller is empty

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

For multi-port configurations, PCTRL_n.port_en is used to enable or disable the input traffic per port.

The controller idleness can be polled first from PSTAT register (wr_port_busy_n and rd_port_busy_n bit fields) and should read as PSTAT==32’b0 (not busy).

The DDRC CAM/pipeline empty status must be polled ((DBGCAM.dbg_wr_q_empty== 1’b1) && (DBGCAM.dbg_rd_q_empty== 1’b1) && (DBGCAM.wr_data_pipeline_empty== 1’b11) && (DBGCAM.rd_data_pipeline_empty== 1’b1)). Also, if the DDR4 retry is enabled by the CRCPARCTRL1.crc_parity_retry_enable, poll CRCPARSTAT.cmd_in_err_window until it is equal to 0.

If software intervention is enabled by CRCPARCTL1.alert_wait_for_sw, monitor CRCPARSTAT.dfi_alert_err_int and CRCPARSTAT.dfi_alert_err_fatl_int during the polling. If one or more of them are asserted before polling is finished, retry, because the procedure must be completed prior to the subsequent steps. In this mode, it is safe to write the group 3 registers. Enable the traffic by writing 1’b1 to PCTRL_n.port_en.