High Performance PS to PL AXI Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Two high-performance interfaces, M_AXI_HPM0_FPD and M_AXI_HPM1_FPD (data width selectable to be 32/64/128-bit), are provided to allow the CPUs, DMAs, and PCIe to push large amount of data from the PS to the PL. They are also AXI FIFO interfaces that enable the following.

Conversion from the AXI3 to AXI4 protocols as the PL interfaces are AXI4 compliant, while the internal PS interfaces are AXI3 compliant. AXI4 access in the PL is limited to a burst length of 16.

Clock domain crossing between PS and PL interfaces. A single clock is available in the PL interface for read and write operation.

The PS interconnect assigns the master ID bits and transfers these bits on the AxUSER bits of the associated AXI transaction. The AxUSER[9:0] bits correspond to the master IDs listed in Table: Master IDs List. The AxUSER[15:10] bit might be used for other purposes by the system including coherency and transaction poisoning.