High Throughput (Best Effort) Masters

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

These masters can tolerate longer latency but they must have very high throughput to achieve an architectural goal. The typical examples are the GPU and PL. Due to the nature of these devices, they could issue a data request long before it is used to effectively cancel out latency. However, the interconnect must be able to accept multiple outstanding requests at the same time.