Host Interface (Master/Slave)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The host controller interfaces to the system bus using the AXI master and slave interface.

The slave bus is used to access the registers inside the host controller. Also, when operating in PIO mode, the driver can access the SD data port register through this interface. This is the PIO method in which the host driver transfers data using the buffer data port register. The slave bus supports only single transfer access (no burst support). Also, in the case of the AXI interface, the slave bus supports only one outstanding read/write transaction.

The master bus is used by the DMA controller (when using DMA or ADMA2 modes). The DMA controller uses the master DMA interfaces to transfer data between the internal buffer and the system memory and vice versa. The DMA controller also uses the master interface to fetch the descriptors while operating in ADMA2 mode.