The NAND flash memory signals are routed to the MIO pins as listed in Table: NAND Interface Signals.
Table 25-2: NAND Interface Signals
NAND Signals
|
MIO Pins
|
I/O
|
Signal Name
|
Default Value
|
Option 1
|
Option 2
|
Chip enable 1
|
9
|
26
|
O
|
NFC_CE[1]
|
-
|
Ready/busy 0
|
10
|
27
|
I
|
NFC_RB_n[0]
|
0
|
Ready/busy 1
|
11
|
28
|
I
|
NFC_RB_n[1]
|
0
|
Data strobe
|
12
|
32
|
I/O
|
NFC_DQS_OUT
|
-
|
Chip enable 0
|
13
|
13
|
O
|
NFC_CE[0]
|
-
|
Command latch enable
|
14
|
14
|
O
|
NFC_CLE
|
-
|
Address latch enable
|
15
|
15
|
O
|
NFC_ALE
|
-
|
Data/address/CMD 0
|
16
|
16
|
I/O
|
NFC_DQ_OUT[0]
|
0
|
Data/address/CMD 1
|
17
|
17
|
I/O
|
NFC_DQ_OUT[1]
|
0
|
Data/address/CMD 2
|
18
|
18
|
I/O
|
NFC_DQ_OUT[2]
|
0
|
Data/address/CMD 3
|
19
|
19
|
I/O
|
NFC_DQ_OUT[3]
|
0
|
Data/address/CMD 4
|
20
|
20
|
I/O
|
NFC_DQ_OUT[4]
|
0
|
Data/address/CMD 5
|
21
|
21
|
I/O
|
NFC_DQ_OUT[5]
|
0
|
Write enable
|
22
|
22
|
O
|
NFC_WE_B
|
-
|
Data/address/CMD 6
|
23
|
23
|
I/O
|
NFC_DQ_OUT[6]
|
0
|
Data/address/CMD 7
|
24
|
24
|
I/O
|
NFC_DQ_OUT[7]
|
0
|
Read enable
|
25
|
25
|
O
|
NFC_RE_n
|
-
|
This Figure shows a block diagram of a single NAND flash memory connected to the NAND controller.
Figure 25-2: Single NAND Device Wiring Diagram
X-Ref Target - Figure 25-2
|
This Figure shows a block diagram of two NAND flash memories connected to the NAND controller.
Figure 25-3: Two NAND Flash Device Wiring Diagram
X-Ref Target - Figure 25-3
|