IOP Bus Masters

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The bus requests from the peripheral masters will be routed to DDR memory (non-coherent) or through the CCI (coherent). The route for the eight IOP masters are individually selected by the IOU_INTERCONNECT_ROUTE register.