IPI Interrupts and Message Buffers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The heterogeneous multiprocessor system uses the inter-processor interrupt (IPI) structure to exchange short interrupt-driven messages between processors in the system. The IPI architecture allows the passing of messages across the system without the complications of autonomous read-write transactions and polling inefficiency.

Four channels assigned to target the PMU.

Seven channels can be assigned to target RPU core 0, RPU core 1, the APU MPCore, four processors in the PL, and four channels to the PMU (in addition to the dedicated channels).

Register access is restricted to a processor by the XPPU protection unit.

Note:   The IPI channel registers can be owned by any of the masters except the interrupts for the PMU channels are only routed to the PMU.

Processor communications include both an IPI interrupt structure and memory buffers to exchange short private 32B messages between eight IPI agents — the PMU, RPU, APU, and PL processors. Access to the interrupt registers and message buffers is protected by the XPPU to give exclusive access to the AXI transactions of the agents.

In a typical situation, the sender writes a 32-byte request message and generates an interrupt to the receiver. The receiver can write a response message and clear the interrupt that is observed by the sender. The communications process uses both the IPI interrupt structure and the message buffers. There are eleven interrupt channels and eight sets of message buffers.

The interrupt channels are as follows.

°Seven interrupts default to APU MPCore, RPU0, RPU1, and PL {0:3}, but can be reprogrammed to any processor because they are distributed to all four system interrupt controllers.

°Four interrupts are hardwired to the PMU interrupt controller, IPI channels {3:6}.

Message buffers provide exclusive communications between each sender and each receiver.

°Seven sets of assignable message buffers.

°One set of buffers dedicated to the PMU.

°Each set has eight request and eight response buffers (16 buffers per set, 128 total buffers).

The PMU special considerations are as follows.

Four sets of IPI interrupt registers for one processor.

The PMU IPI 0 interrupt instructs the PMU to enter sleep mode.

One set of message buffers are used for all four PMU interrupts.

The IPI interrupts and message buffers are independent hardware functions that are associated by software programming. There are default owners and an implied association between the interrupt registers and message buffers. Only the PMU interrupts are fixed in hardware.

The sender can post multiple interrupt requests and have different communication protocols with each target. The assignment and use of the non-PMU interrupts and the entire message passing architecture can be programmed as needed by the system architecture. The reset default conditions and software conventions in the SDK define a starting state for the system.