IRQ Interrupt

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The AMS interrupt registers are programmed to enable alarm signals to generate IRQ 88 to the GICs and PL. The IRQ interrupt can also be generated when the PS SYSMON conversion or sequence is finished, or there is an address decode error on one of the three register sets. There are two interrupt register sets for the following sources.

ISR_{0, 1} are read/write and provide the interrupt status (before the mask) corresponding with each alarm signal. Writing a “1” to a status bit clears the interrupt.

IMR_{0, 1] are read-only and provide a mask that is used after the status and before the wide OR gate to generate IRQ 88.

IER_{0, 1} and IDR_{0,1} are write-only to set and clear bits in the IMR registers.

ITR_{0, 1} are write-only to enable software to trigger an individual interrupt bit in ISR.