Impedance Calibration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PHY includes calibration I/O cells and finite state machine logic to automatically compensate output drive strength and on-die termination strength, adjusting for variations in process, voltage, and temperature. The Impedance Control Status Registers (ZQnSR) provide additional debugging information. ZQ0SR shows the results of calibration for address, command, and control I/Os. ZQ1SR shows the results of calibration for data, strobe, and mask I/Os. Table: Impedance Control Status Register (ZQnSR) lists the fields within ZQnSR.

Impedance calibration failures can be caused by an open or short on the PS_DDR_ZQ pin.  Double check to ensure PS_DDR_ZQ is connected to GND with a 240Ω resistor. There should be separate 240Ω resistors at the FPGA and the DRAM.

Table 17-6:      Impedance Control Status Register (ZQnSR)

Bits

Name

Description

Address

[1:0]

ZPD

Output impedance pull-down calibration status. Valid status encodings are:

2b00 = Completed with no errors

2b01 = Overflow error

2b10 = Underflow error

2b11 = Calibration in progress

0xFD08069C

and

0xFD0806BC

[3:2]

ZPU

Output impedance pull-up calibration status. Valid status encodings are:

2b00 = Completed with no errors

2b01 = Overflow error

2b10 = Underflow error

2b11 = Calibration in progress

0xFD08069C

and

0xFD0806BC

[5:4]

OPD

On-die termination (ODT) pull-down calibration status. Valid status encodings are:

2b00 = Completed with no errors

2b01 = Overflow error

2b10 = Underflow error

2b11 = Calibration in progress

0xFD08069C

and

0xFD0806BC

[7:6]

OPU

On-die termination (ODT) pull-up calibration status. Valid status encodings are:

2b00 = Completed with no errors

2b01 = Overflow error

2b10 = Underflow error

2b11 = Calibration in progress

0xFD08069C

and

0xFD0806BC

[8]

ZERR

Impedance calibration error: if set, indicates that there was an error during impedance calibration.

0xFD08069C

and

0xFD0806BC

[9]

ZDONE

Impedance calibration done: indicates that the first round of impedance calibration has completed. Any time impedance calibration is restarted, this bit goes back to 0 until all segments are recalibrated, following which this bit returns to 1.

0xFD08069C

and

0xFD0806BC

[10]

PU_DRV_SAT

Pull-up drive strength code saturated due to drive strength adjustment setting in ZQnPR register. Is non-zero only in LPDDR4 mode. If this is set to 1'b1, the adjustment factor or ZPROG setting for the corresponding segment needs to be scaled.

0xFD08069C

and

0xFD0806BC

[11]

PD_DRV_SAT

Pull-down drive strength code saturated due to drive strength adjustment setting in ZQnPR register. Is non-zero only in DDR4 mode. If this is set to 1'b1, the adjustment factor or ZPROG setting for the corresponding segment needs to be scaled.

0xFD08069C

and

0xFD0806BC

[12]

PU_ODT_SAT

Pull-up termination strength code saturated due to drive strength adjustment setting in ZQnPR register. Is non-zero only in DDR4 mode. If this is set to 1'b1, the adjustment factor or ZPROG setting for the corresponding segment needs to be scaled.

0xFD08069C

and

0xFD0806BC

 

[13]

PD_ODT_SAT

Pull-down termination strength code saturated due to drive strength adjustment setting in ZQnPR register. Is non-zero only in LPDDR4 mode. If this is set to 1'b1, the adjustment factor or ZPROG setting for the corresponding segment needs to be scaled.

0xFD08069C

and

0xFD0806BC