Implementation Notes

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

If the suggested use-model requirements are satisfied, attaching FCI to SRC/DST is not required.

When FCI is enabled, both the AXI read and write command use the same burst length SRC AXI length (ARLEN).

When the SRC and DST descriptor payloads are not aligned to the bus width, the number of read and write transactions could be different.

The size of the first and last transaction can be different based on the alignment of the read and write payload.

One credit means one AXI read or write transaction. The size of the transaction can vary based on the 4k boundary crossing and over fetch disable. The DMA channel never generates a transaction larger than the programmed ARLEN.

Read/write transactions can be controlled using more than one mechanism. A channel might not generate a transaction, even if it has credits, due to other channel control parameters.

°Rate control counter

°Outstanding transaction count