Individual MPCore Shutdown Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In the individual MPCore shutdown mode, the PDCPU power island for an individual MPCore is shut down and all states are lost.

Use these steps to power down the MPCore.

1.Disable the data cache, by clearing the SCTLR.C bit, or the HSCTLR.C bit if in Hyp mode. This prevents more data cache allocations and causes cacheable memory attributes to change to normal, non-cacheable. Subsequent loads and stores do not access the L1 or L2 caches.

2.Clean and invalidate all data from the L1 data cache. The L2 duplicate snoop tag RAM for this MPCore is empty. This prevents any new data cache snoops or data cache maintenance operations from other MPCore in the cluster being issued to this core.

3.Disable any data coherency with other MPCores in the cluster by clearing the CPUECTLR.SMPEN bit. Clearing the SMPEN bit enables the MPCore to be taken out of coherency by preventing the MPCore from receiving cache or TLB maintenance operations broadcast by other MPCores in the cluster.

4.Execute an ISB instruction to ensure that all of the register changes from the previous steps are completed.

5.Execute a DSB SY instruction to ensure completion of all cache, TLB, and branch predictor maintenance operations issued by any MPCore in the cluster device before the SMPEN bit is cleared.

6.Execute a WFI instruction and wait until the STANDBYWFI output is asserted to indicate that the MPCore is in an idle and a low-power state.

7.Deassert DBGPWRDUP Low. This prevents any external debug access to the MPCore.

8.Activate the MPCore output clamps.

9.Remove power from the PDCPU power domain.

To power up the MPCore, apply the following sequence.

1.Assert nCPUPORESET Low. Ensure DBGPWRDUP is held Low to prevent any external debug access to the MPCore.

2.Apply power to the PDCPU power domain. Keep the state of the signals nCPUPORESET and DBGPWRDUP Low.

3.Release the MPCore output clamps.

4.Deassert the resets.

5.Set the SMPEN bit to 1 to enable snooping into the MPCore.

6.Assert DBGPWRDUP High to allow external debug access to the MPCore.

7.If required, use software to restore the state of the MPCore to its the state prior to power-down.