Inject Fault

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Enable error response by setting the third bit of the ocm.OCM_ERR_CTRL register.

2.Enable ECC by setting the zeroth bit of the ocm.OCM_ECC_CTRL register.

3.To only detect single bit errors, set the first bit of the ocm.OCM_ECC_CTRL register. By default this bit is zero and it indicates that single-bit errors are corrected.

4.To inject an error on every write after fault injection count cycle, set the second bit of the ocm.OCM_ECC_CTRL register. If a zero is programmed for the same bit in the register, then only a single fault is injected.

5.The fault injection count must be programmed by setting the required value in the first 24 bits of the ocm.OCM_FI_CNTR register.

6.A fault can be injected into the syndrome bits using the ocm.OCM_FI_SY register. Faults in the data words can be injected using the ocm.OCM_FI_D{0:3} registers.

7.Interrupts can be enabled for different errors by setting the required bits of the ocm.OCM_IEN register.

8.Unwanted interrupts can be disabled by setting the required bits of the ocm.OCM_IDS register.

9.Reading the ocm.OCM_IMR register gives information regarding the type of interrupts that are masked out. This is a read-only register and reflects the settings done on the ocm.OCM_IEN and ocm.OCM_IDS registers.