Instruction Fetch Unit

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The instruction fetch unit (IFU) contains the instruction cache controller and its associated linefill buffer. The Cortex-A53 MPCore instruction cache is 2-way set associative and uses virtually-indexed physically-tagged (VIPT) cache lines holding up to 16 A32 instructions, 16 32-bit T32 instructions, 16 A64 instructions, or up to 32 16-bit T32 instructions.

The IFU obtains instructions from the instruction cache or from external memory and predicts the outcome of branches in the instruction stream, and then passes the instructions to the data-processing unit (DPU) for processing.