This example assumes the input PS_REF_CLK frequency is 50 MHz, the [FBDIV] value is 40, and the output divider is turned on. The output clock is calculated to be 50 MHz x 40/2 = 1000 MHz. For a new frequency of 1600 MHz, the [FBDIV] value is switched to 32 and the output divider is turned off. This example uses the APLL.
Note: Before reprogramming the PLL clock output frequency, check that the downstream clocks are in a safe state before releasing. For instance, if the APU DIVISOR is set to 2.
1.Program the new FBDIV, CLKOUT value (do not modify other values in the APLL_CTRL register).
Set APLL_CTRL = 0000_2000h: [DIV2] = 0, [FBDIV] = 20h.
2.Program the helper data for APLL_CFG using the helper data in Table: PLL Integer Feedback Divider Helper Data Values.
3.Program the bypass.
Set APLL_CTRL = 0000_2008h: [BYPASS] = 1.
4.Assert reset. This is when the new data is actually captured into the PLL.
Set APLL_CTRL = 0000_2009h: [RESET] = 1.
Set APLL_CTRL = 0000_2008h: [RESET] = 0.
6.Check for LOCK. Wait until: PLL_STATUS [APLL_LOCK] = 1
Set APLL_CTRL = 0000_2000h: [BYPASS] = 20h.
The PLL output clock is set to 1600 MHz.