Integrated Block for PCI Express

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The integrated block for PCIe complies with the PCI Express base specification, rev. 2.1 and consists of the physical, data link, and transaction layers. The protocol uses packets to exchange information between layers. Packets are formed in the transaction and data link layers to carry information from the transmitting component to the receiving component. Information is added to the transmitted packet that is required to handle the packet at specific layers.

The functions of the protocol layers include the following.

Generating and processing of TLPs.

Flow-control management.

Initialization and power management functions.

Data protection.

Error checking and retry functions.

Physical link interface initialization.

Maintenance and status tracking.

The integrated block for PCI Express supports up to 4-lane 2.5 GT/s and 5.0 GT/s PCI Express Endpoint and Root Port configurations.

The integrated block for PCIe provides PIPE interface for connection to the gigabit transceivers. The PIPE interface runs at 250 MHz in Gen2 (5 Gb/s, per lane, per direction) mode or 125 MHz in Gen1 (2.5 Gb/s, per lane, per direction) mode.

The PS-GTR transceivers in the processing system (PS) are used for serialization/deserialization (SerDes) purposes. The high-speed transceivers are used through the multiplexer switch and are shared with other blocks (such as DisplayPort, SATA, USB, and GEM) in the PS.

Further details on transceivers are available in PS-GTR Transceivers.

 

IMPORTANT:   The AXI streaming and sideband signals between the AXI-PCIe bridge and the integrated block for PCI Express are not directly accessible. Every PCIe transfer initiated in the AXI domain passes through the AXI-PCIe bridge.

PCI Express uses a credit-based flow control mechanism. The integrated block for PCIe can be programmed to advertise credit information based on the buffering used. This is set by default to optimal values (based on the RAMs used in the implementation). The values are available in the PCIE_ATTRIB register space for various flow control credit options.

 

IMPORTANT:   In both Endpoint and Root Port modes, the integrated block for PCIe advertises infinite completions; finite completions are not supported.

 

IMPORTANT:   When integrated block for PCIe is enabled in root port mode, enabling coherency features through CC-400 using AxACACHE overrides in AXI-PCIe Bridge registers and enabling SMMU are not supported.