Integrated Block for PCIe Domain

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Bridge and DMA registers are accessed over the integrated block for PCIe at fixed offsets in the PCIe BAR region. The cfg_dma_reg_bar is zero (by default) making all BAR0 transactions consumable by the bridge.

PCIe access to bridge registers is disabled (by default) (cfg_disable_pcie_bridge_reg_access).

PCIe access to DMA channel registers is controlled through cfg_disable_pcie_dma_reg_access. This access is enabled by default.

The registers in the bridge are prefetchable. The BAR targeting these registers (BAR0 by default) can be marked prefetchable.