Interconnect Clock Generators

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are five clock generators for the AMBA interconnect structure. Each clock generator has a similar architecture with one divisor and one clock activate control as shown in This Figure. The control registers are listed in Table: AMBA Interconnect Clock Control.

LPD_LSBUS_CLK: clocks the slave switches and the APB interfaces in the LPD, including LPD_SLCR, XMPU, CSU DMA, LPD DMA, DAP, eFUSE, RPU, IPI, OCM, and APM.

IOU_SWITCH_CLK: clocks the AXI interfaces for the IOP peripherals in LPD.

LPD_SWITCH_CLK: clocks the AXI interfaces for the non-IOP interfaces in LPD.

TOPSW_LSBUS_CLK: clocks the slave switches and the APB interfaces in the FPD.

TOPSW_MAIN_CLK: clocks the AXI interfaces in the FPD including the CCI, DDR ports, SMMU ports, and the SIOU DMA masters. Also clocks the PS-PL AXI interfaces on the FPD side.