Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Separate clocks on each interface to ease integration

Wide data interfaces on input and output with configurable support for 1, 2, or 4 lanes

Ability to specify number of LLR values on each lane on either a block-by-block basis, or transfer basis

Separate inputs to specify control parameters and receive status output on a block-by-block basis