Interrupt Architecture

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The interrupt architecture includes eleven sets of registers with six registers per set. Each set is divided between sending an interrupt (TRIG and OBS) and receiving an interrupt (ISR, IMR, IER, and IDR). Access to each set of interrupt registers is protected by eight of the 64 KB apertures in the XPPU. Only eight apertures are needed because the four PMU interrupt registers are all within one 64 KB address space.

To send an interrupt, the sender writes a 1 to the bit in its trigger register that corresponds to the receiving master. The receiver sees the interrupt in its status register, ISR, in the bit field that corresponds to the sender. The sender can observe the state of the interrupts that it triggered to the receivers using its observation register (OBS). The receiver agent processes interrupts in a normal manner. The registers and signal routings are shown in This Figure.

Figure 13-4:      Sender-Receiver Interrupt Functions

X-Ref Target - Figure 13-4

X19836-sender-receiver-interrupt-functions.jpg