This Figure shows the block diagram of the processor interrupts. The shared peripheral interrupts are generated from various subsystems that include the I/O peripherals in the PS and logic in the PL. The PCIe MSI are handled by the controller for PCIe by decoding the MSI into a bit-vector and then asserting a sideband interrupt. To guarantee PCIe ordering, the controller for PCIe must wait for the completion of previously outstanding (inbound) writes before asserted an MSI interrupt. Also, the controller for PCIe must ensure that the MSI buffer, which holds the MSI information after asserting interrupt to CPU, does not end up stalling the PCIe inbound traffic (which can cause deadlock).