Interrupt Mask Register

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each bit in the interrupt mask register (IMR) corresponds to a bit in the interrupt status register (ISR). If bit [i] in the interrupt mask register is set, the corresponding bit in the interrupt status register is ignored. Otherwise, an interrupt is generated whenever bit [i] in the interrupt status register is set. Bits in the IMR mask register are set through a write to the interrupt disable register and are cleared by a write to the interrupt enable register. All mask bits are set (interrupts disabled) after reset. The interrupt mask register has the same bit field order as the interrupt status register.