Interrupt Mask Register (IMR_REG)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The mask register is read-only. When a bit reads as a 1, it means an active interrupt from the status register is masked and it does not propagate to the GICP_PMU_IRQ_STATUS register. The default (reset) state is 1, implying all interrupts are masked.